The present invention relates to efficient design of cell arrays, particularly integrated circuit memory cell arrays.
FIG. 1 shows a prior design of a memory cell array with supporting circuitry. A power source 101 is coupled to a precharge array 102. Precharge array 102 is coupled to a memory cell array 106 through a series of column connector lines 104. Memory cell array 106 is coupled to a decoder 108 also through column connector lines 104. The contents of an addressed memory cell from memory cell array 106 appears on an output 109. The size of the array and the number of output lines within output 109 may vary. For example, if memory cell array 106 has 64 rows and 64 columns, decoder 108 could be a 64 to 1 decoder. On the other hand, if it is desired to address more than one memory cell at a time, then decoder 108 could be, for instance, a 64 by 8 decoder for 8-bit byte addressable memory or a 64 by 16 decoder for 16-bit word addressable memory.
FIG. 2 is a schematic of two memory cells within memory cell array 106. A memory cell 203 and a memory cell 204 of memory cell array 106 are used as examples to illustrate how memory cells within memory cell array 106 are addressed. A control line 103 turns on a transistor 201, a transistor 202 and also transistors for every column of memory cells within memory array 106. This charges a capacitor 205 within memory cell 203, a capacitor 206 within memory cell 204 and also capacitors within every memory cell within memory cell array 106. After the capacitors are charged control line 103 turns off transistors 201, 202 and also the transistors for every column of memory cells within array 106.
In order to select a row of memory cells, a word line corresponding to that row of memory cells is selected. For instance, a wordline 105 is selected which turns on a transistor 207, a transistor 208 and other transistors within memory cells within the selected row. Each memory cell stores a logic 1 or a logic 0. For instance, in FIG. 2 memory cells 203 and 204 are read only memory (ROM) cells. A terminal 210 of memory cell 204 is grounded so that when transistor 208 is turned on, capacitor 206 is discharged and a column line 104b of column lines 104 is at logic 0. On the other hand, a terminal 209 of memory cell 203 is open so that when transistor 207 is turned on, capacitor 205 remains charged and a column line 104a of column lines 104 is at logic 1. Column lines 104a and 104b and all other column lines within column lines 104 are then coupled into decoder 108 which selects one or more column lines within column lines 104 to couple to output 109 as described above.
The memory cell array design of FIG. 1 is not completely efficient. For instance, when selecting a row, transistors within all memory cells in that row are turned on, discharging many more capacitors than is necessary. FIG. 3 shows another prior design which uses power more efficiently.
In FIG. 3 is shown the memory cell array of FIG. 1 with additional circuitry to form a divided line arrangement. Divided lines 309, 310, 311, and 312 are coupled to wordline 105 through switches 301, 302, 303, and 304, respectively. Switches 301-304 are respectively coupled to an encoder 313 through enable lines 316-319. Address lines 314 and 315 select one enable line from enable lines 316-319. This in turn selects one switch from switches 301-304 and one divided line from divided lines 309-312.
In FIG. 4 switch 302 is shown to be, for instance, a Boolean "NAND" gate 401 coupled to a Boolean "NOT" gate 402. As can be seen, selecting only one divided line at a time limits the number of capacitors within the memory cells which are discharged for each memory access. This limits power consumption, however it also increases chip complexity.